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| www..com INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4014B MSI 8-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 www..com Philips Semiconductors Product specification 8-bit static shift register DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0 to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last three stages (O5 to O7). HEF4014B MSI Operation is synchronous and the device is edge-triggered on the LOW to HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop. When PE is HIGH, data is loaded into the register from P0 to P7 on the LOW to HIGH transition of CP. When PE is LOW, data is shifted to the first position from DS, and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times Fig.1 Functional diagram. HEF4014BP(N): HEF4014BD(F): HEF4014BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI Fig.2 Pinning diagram. See Family Specifications January 1995 2 www..com Philips Semiconductors Product specification 8-bit static shift register HEF4014B MSI January 1995 3 Fig.3 Logic diagram. www..com Philips Semiconductors Product specification 8-bit static shift register PINNING PE P0 to P7 DS CP parallel enable input parallel data inputs serial data input clock input (LOW to HIGH edge-triggered) HEF4014B MSI O5 to O7 buffered parallel outputs from the last three stages FUNCTION TABLES Serial operation INPUTS n 1 2 3 6 7 8 CP DS D1 D2 D3 X X X X PE L L L L L L X O5 X X X D1 D2 D3 OUTPUTS O6 X X X X D1 D2 no change O7 X X X X X D1 Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition Dn = either HIGH or LOW n = number of clock pulse transitions n 1 CP Parallel operation INPUTS DS X X PE H X O5 P5 OUTPUTS O6 P6 no change O7 P7 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 900 fi + (foCL) x VDD2 4 300 fi + (foCL) x VDD2 12 000 fi + (foCL) x VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 www..com Philips Semiconductors Product specification 8-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Set-up times PE CP 10 15 5 10 15 5 DS CP 10 15 5 Pn CP Hold times PE CP 10 15 5 10 15 5 DS CP 10 15 5 Pn CP Minimum clock pulse width; LOW 10 15 5 10 15 Maximum clock pulse frequency 5 10 15 fmax tWCPL thold thold thold tsu tsu tsu 40 25 15 35 25 25 35 25 25 25 20 15 30 20 15 30 20 15 70 30 24 6 15 20 tTLH tTHL tPLH tPHL 130 55 40 115 50 40 60 30 20 60 30 20 10 5 0 -5 -5 0 -5 -5 0 -5 0 0 15 10 7 15 10 7 35 15 12 13 30 40 260 110 80 230 100 80 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz SYMBOL MIN. TYP. MAX. HEF4014B MSI TYPICAL EXTRAPOLATION FORMULA 103 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL see also waveforms Fig.4 January 1995 5 www..com January 1995 6 Fig.4 Waveforms showing minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and P to CP. Set-up and hold times are shown as positive values but may be specified as negative values. APPLICATION INFORMATION Some examples of applications for the HEF4014B are: * Parallel-to-serial converter * Serial data queueing * General purpose register Philips Semiconductors 8-bit static shift register HEF4014B MSI Product specification |
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